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VLSI LAB VIVA QUESTIONS WITH ANSWERS PDF

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VLSI Lab Viva questions and answ er s 1. What is Intrinsic and Extrinsic Semiconductor? The pure Silicon is known as Intrinsic Semiconductor. When impurity is. VLSI Lab viva question with answersNote: First of all, we are very thankful to the Only-Vlsi (myavr.info) for thesequestion. VLSI viva questions and answers pdf VLSI lab viva questions with answers pdf VLSI Mcqs interview questions jntu 6th 7th sem ECE questions.


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VTU - VLSI Lab Viva Questions - Part 1. Vlsi questions. Why don?t we use just one NMOS or PMOS transistor as a transmission gate? Because. 6/1/ VLSI Lab Viva questions and answers PDF | sushanth kj myavr.info myavr.info Top 17 VLSI Interview Questions & Answers 10) Explain why present VLSI circuits use MOSFETs instead of BJTs? Download PDF.

Answer Mealy FSM uses only input actions, i. The use of a Mealy FSM leads often to a reduction of the number of states. Moore FSM uses only entry actions, i. The advantage of the Moore model is a simplification of the behavior. What are various types of state encoding techniques? Explain them. Answer One-Hot encoding: Each state is represented by a bit flip-flop.

Engineering Questions

If there are four states then it requires four bits four flip-flops to represent the current state. The valid state values are , Citystudentsgroup. If the value is , then it means second state is the current state. One-Cold encoding: Same as one-hot encoding except that '0' is the valid value.

300+ TOP VLSI LAB VIVA Questions and Answers

The valid state values are , , , and Binary encoding: Each state is represented by a binary code. Gray encoding: Each state is represented by a Gray code. Answer Clock skew is a phenomenon in synchronous circuits in which the clock signal sent from the clock circuit arrives at different components at different times. This can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock.

There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the clock reaches the receiving register later than it reaches the register sending data to the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register.

Design a 4-bit comparator circuit. Now, how do you convert it to XNOR without inverting the output? Define Metastability. Answer If there are setup and hold time violations in any sequential circuit, it enters a state where its output is unpredictable, this state is known as metastable state or quasi stable state, at the end of metastable state, the flip-flop settles down to either logic high or logic low.

This whole process is known as metastability.

Compare and contrast between 1's complement and 2's complement notation. What are set up time and hold time constraints?

Answer Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge. Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable, which is known as as metastable state or quasi stable state. At the end of metastable state, the flip-flop settles down to either logic high or logic low. Give a circuit to divide frequency of clock cycle by two.

Explain different types of adder circuits. Give two ways of converting a two input NAND gate to an inverter.

Draw a Transmission Gate-based D-Latch. Design a FSM which detects the sequence from a serial line without overlapping. Design a FSM which detects the sequence from a serial line with overlapping. Give the design of 8x1 multiplexer using 2x1 multiplexers. Design a counter which counts from 1 to 10 Resets to 1, after Design a circuit which doubles the frequency of a given input clock signal.

Implement a D-latch using 2x1 multiplexer s. Give the excitation table of a JK flip-flop.

What is race condition? Give 1's and 2's complement of Answer 1's complement: 2's complement: Citystudentsgroup. Design a decoder. Design a 3 bit Gray Counter. Give the differences between them. Answer Programmable Logic Array is a programmable device used to implement combinational logic circuits.

The PLA has a set of programmable AND planes, which link to a set of programmable OR planes, which can then be conditionally complemented to produce an output. Due to fixed OR plane PAL allows extra space, which is used for other basic logic devices, such as multiplexers, exclusive-ORs, and latches.

Most importantly, clocked elements, typically flipflops, could be included in PALs. PALs are also extremely fast. What is LUT? An n-bit look-up table can be implemented with a multiplexer whose select lines are the inputs of the LUT and whose inputs are constants.

VLSI Lab Viva Questions and Answers 1

An n-bit LUT can encode any n-input Boolean function by modeling such functions as truth tables. What is the significance of FPGAs in modern day electronics? Applications of FPGA. This helps for faster and cheaper testing.

These binary numbers can combine billion of machines into one machines or circuit and operate those machines by performing arithmetic calculations and sorting operations.

A sequential circuit is a circuit which is created by logic gates such that the required logic at the output depends not only on the current input logic conditions, but also on the sequences past inputs and outputs. In Verilog, circuit components are prepared inside a Module. It contains both behavioral and structural statements. Structural statements signify circuit components like logic gates, counters and micro-processors.

Behavioral statements represent programming aspects like loops, if-then statements and stimulus vectors. The triode and cut-off region are used to function as a switch, while, saturation region is used to operate as an amplifier.

When positive voltage is transmitted across Gate, it causes the free holes positive charge to be pushed back or repelled from the region of the substrate under the Gate. When these holes are pushed down the substrate, they leave behind a carrier depletion region.

Higher the number of stacks, slower the gate will be. So input are restricted to four. A multiplexer is a combination circuit which selects one of the many input signals and direct to the only output.

SCR is a 4 layered solid state device which controls current flow. It is a type of rectifier that is controlled by a logical gate signal.Epitaxy means arranging atoms in single crystal fashion upon a single crystal substrate. There are standard tools available like PayScale which you can use as well. AnswerClick here. In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos.

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